EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 417
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
Table 1–9. Detection Capabilities of the Run-Length Violation Circuit for Arria II Devices
■
Figure 1–32. 10-Bit Receiver Polarity Inversion
Receiver polarity inversion—This feature is available in all functional modes
except PCIe. It offers an optional rx_invpolarity port to dynamically enable the
receiver polarity inversion feature as a workaround to board re-spin or a major
update to the FPGA fabric design when the positive and negative signals of a
serial differential link are accidentally swapped during board layout.
1
Table 1–9
A high value on the rx_invpolarity port inverts the polarity of every bit of the
input data word to the word aligner in the receiver datapath. Because inverting
the polarity of each bit has the same effect as swapping the positive and negative
signals of the differential link, correct data is seen by the receiver. The
rx_invpolarity signal is dynamic and might cause initial disparity errors in an
8B/10B encoded link. The downstream system must be able to tolerate these
disparity errors.
Figure 1–32
wide datapath configuration.
PMA-PCS Interface Width
This generic receiver polarity inversion feature is different from the PCIe
8B/10B polarity inversion feature because it inverts the polarity of the data
bits at the input of the word aligner, whereas the PCIe 8B/10B polarity
inversion feature inverts the polarity of the data bits at the input of the
8B/10B decoder.
lists the detection capabilities of the run-length violation circuit.
10 bit
16 bit
20 bit
shows an example result with the rx_invpolarity feature in a 10-bit
8 bit
Output from Deserializer
0
1
0
1
1
1
1
1
0
0
rx_invpolarity = HIGH
Converted Data to Word Aligner
Minimum
Run Length Violation Detector Range
10
4
5
8
Arria II Device Handbook Volume 2: Transceivers
1
0
1
0
0
0
0
0
1
1
Maximum
128
160
512
640
1–31
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