EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 438
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–52
Arria II Device Handbook Volume 2: Transceivers
Figure 1–51
functional mode with an 8-bit wide PMA-PCS interface.
Figure 1–51. Transceiver Configurations in Basic Mode with an 8-Bit Wide PMA-to-PCS Interface
Notes to
(1) The 10-bit configuration is listed in
(2) The maximum data rate specification shown in
(3) When you enable byte SERDES, the maximum data is 3G; otherwise, it is 1.92G.
(Note 1)
Functional Mode
Data Rate (2)
Number of Channels
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES (3)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz) (2)
TX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
RX PCS Latency
(FPGA Fabric-Transceiver
Interface Clock Cycles)
specifications for other speed grades offered, refer to the
Figure
shows the Arria II GX and GZ transceiver configurations allowed in Basic
1–51:
Disabled
Disabled
11 - 13
4 - 5.5
Figure
8-Bit
240
75-
Manual Alignment
Disabled
Disabled
1–52.
(16-Bit)
Disabled
16-Bit
187.5
4 - 5.5
Figure 1–51
37.5-
7 - 9
Enabled
Enabled
8 - 10
Disabled
16-Bit
187.5
Device Datasheet for Arria II Devices
Chapter 1: Transceiver Architecture in Arria II Devices
37.5-
4 - 5.5
is valid only for the -3 speed grade devices. For data rate
Basic 8-Bit PMA-PCS Interface Width
Disabled
Disabled
11 - 13
4 - 5.5
8-Bit
240
75-
Disabled
Disabled
(16-Bit)
Bit Slip
0.6 - 3.0 Gbps
×1, ×4, ×8
Disabled
Enabled
December 2010 Altera Corporation
16-Bit
187.5
37.5-
4 -5.5
7 - 9
Disabled
Disabled Disabled
8-Bit
3 - 4
240
3 - 4
75-
chapter.
Disabled
Disabled
Disabled
Enabled
Functional Modes
Enabled
3 - 4.5
16-Bit
187.5
3 - 4.5
37.5-
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