EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 194

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–36
Arria II Device Handbook Volume 1: Device Interfaces and Integration
I/O Bank Restrictions
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Arria II devices.
Non-Voltage-Referenced Standards
Each Arria II device I/O bank has its own VCCIO pins and supports only one V
I/O bank can simultaneously support any number of input signals with different I/O
standard assignments, as shown in
For output signals, a single I/O bank supports non-voltage-referenced output signals
that drive at the same voltage as V
value, it can only drive out the value for non-voltage-referenced signals. For example,
an I/O bank with a 2.5-V V
and 3.0-V LVCMOS inputs (but not output or bidirectional pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Arria II GX I/O bank has a
dedicated VREF pin while Arria II GZ I/O banks supports multiple VREF pins feeding a
common VREF bus. The number of available VREF pins increases as device density
increases. For Arria II GZ devices, if these pins are not used as VREF pins, they cannot
be used as generic I/O pins and must be tied to V
have a single V
Arria II GX I/O banks featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards use the same
V
For Arria II GZ devices, voltage-referenced input standards use their own V
as the power source. This feature allows you to place voltage-referenced input signals
in an I/O bank with a V
input pins in an I/O bank with 2.5-V V
with R
input standard.
Voltage-referenced bidirectional and output signals must be the same as the V
voltage of the I/O bank. For example, you can only place SSTL-2 output pins in an
I/O bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
R EF
setting.
T
OCT enabled requires the V
CCIO
voltage level and a single V
CCIO
CCIO
CCIO
.
of 2.5 V or below. For example, you can place HSTL-15
setting can support 2.5-V standard inputs and outputs
CCIO
Table 6–1 on page
CCIO
. Because an I/O bank can only have one V
CCIO
of the I/O bank to match the voltage of the
. However, the voltage-referenced input
REF
CCIO
voltage level at a given time.
6–2.
CCIO
or GND. Each bank can only
Chapter 6: I/O Features in Arria II Devices
and 0.75-V V
December 2010 Altera Corporation
CCIO
and a 0.9-V V
Design Considerations
REF
.
CCPD
CCIO
CCIO
REF
level
. An
CCIO
.