EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 534
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–44
Arria II Device Handbook Volume 2: Transceivers
1
This configuration uses two FPGA clock resources (global, regional, or both), one for
the tx_clkout[0] signal, and one for the tx_clkout[2] signal.
This example assumes channels 0 and 1, driven by CMU0 PLL in a transceiver block,
are identical. Also, channels 2 and 3, driven by CMU1 PLL in the same transceiver
block, are identical. In this case, the Quartus II software automatically drives the
read port of the receiver phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the read port of the receiver phase
compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the
tx_clkout[0] signal to latch the receiver data and status signals from channels 0
and 1 in the FPGA fabric. Use the tx_clkout[2] signal to latch the receiver data
and status signals from channels 2 and 3 in the FPGA fabric.
Example 7: Two Groups of Two Identical Channels in a Transceiver Block
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
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