EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 234

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–38
Figure 7–25. IOE Input Registers for Arria II GX Devices
Notes to
(1) You can bypass each register block in this path.
(2) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(3) This input clock comes from the CQn logic block.
(4) The DQS signal must be inverted for DDR interfaces except for the QDR II+/QDR II SRAM interfaces. This inversion is done automatically if you
Arria II Device Handbook Volume 1: Device Interfaces and Integration
use the Altera external memory interface IPs.
Figure
DQS (2), (4)
DQSn
CQn (3)
7–25:
DQ
Differential
Buffer
Input
datain
Figure 7–25
consists of DDR input registers and resynchronization registers. You can bypass each
block of the input path.
1
0
Double Data Rate Input Registers
Input Reg B
Input Reg A
D
D
DFF
DFF
Resynchronization
Clock
(resync_clk_2x)
(3)
Q
Q
shows the registers available in the Arria II GX input path. The input path
neg_reg_out
I
I
regouthi
Input Reg C
D
DFF
Q
I
regoutlo
(Note 1)
Synchronization Registers
D
D
DFF
DFF
Chapter 7: External Memory Interfaces in Arria II Devices
Q
Q
Arria II External Memory Interface Features
December 2010 Altera Corporation
To Core (rdata0)
To Core (rdata1)