EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 237
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–28. IOE Output and Output-Enable Path Registers for Arria II GZ Devices
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL.
(4) The write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them.
December 2010 Altera Corporation
Half-Rate Clock (3)
Figure
From Core (2)
From Core (2)
(wdata1) (2)
(wdata2) (2)
(wdata0) (2)
(wdata3) (2)
From Core
From Core
From Core
From Core
7–28:
For Arria II GX devices, the output path is designed to route combinatorial or
registered single data rate (SDR) outputs and DDR outputs from the FPGA core.
The output enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications.
Figure 7–28
paths. The path is divided into the HDR block, resynchronization registers, and
output and output-enable registers. The device can bypass each block of the output
and output-enable path.
D
D
D
D Q
D Q
D
Half Data Rate to Single Data Rate
Half Data Rate to Single Data Rate
DFF
DFF
DFF
DFF
DFF
DFF
Q
Q
Q
Q
Output-Enable Registers
Output Registers
shows the registers available in the Arria II GZ output and output-enable
D
D
D
DFF
DFF
DFF
Q
Q
Q
0
1
0
1
0
1
Clock (4)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Write
OE Reg B
OE Reg A
Output-Enable Registers
Output Reg Ao
Output Reg Bo
Double Data Rate
(Note 1)
D Q
D Q
D Q
D Q
DFF
DFF
DFF
DFF
OE
OE
Double Data Rate
1
0
Output Registers
1
0
OR2
TRI
DQ or DQS
7–41
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