EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 289
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
- Current page: 289 of 692
- Download datasheet (22Mb)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Configuration Schemes
Configuration Schemes
Table 9–6. Configuration Schemes for Arria II GX Devices (Part 1 of 2)
December 2010 Altera Corporation
FPP
FPP with design security feature,
decompression, or both enabled
PS
User Mode
MSEL Pin Settings
Configuration Scheme
1
1
An optional INIT_DONE pin is available, which signals the end of initialization and the
start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. When
initialization is complete, the device enters user mode. In user-mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
The following sections describe configuration schemes for Arria II devices.
Select the configuration scheme by driving the Arria II device MSEL pins either high or
low, as listed in
V
Altera recommends hardwiring the MSEL[] pins to V
MSEL[3..0] pins have 5-kΩ internal pull-down resistors that are always active.
During POR and during reconfiguration, the MSEL pins must be at LVTTL V
levels to be considered logic low and logic high, respectively.
To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL[] pins to V
drive the MSEL[] pins by a microprocessor or another device.
For
MSEL[3..0] for Arria II GX devices and MSEL[2..0] for Arria II GZ devices as listed in
Table 9–6
CCPD
Figure 9–1 on page 9–12
and V
(2)
and
CCPGM
Table
Table 9–6
CCPD
power supplies for Arria II GX and GZ devices, respectively.
9–7, respectively.
MSEL3
/V
0
0
0
1
0
1
1
1
CCPGM
and
through
or GND without pull-up or pull-down resistors. Do not
Table
MSEL2
0
1
0
0
0
0
0
0
9–7. The MSEL input buffers are powered by the
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure 9–30 on page
MSEL1
0
1
0
0
1
0
1
1
MSEL0
CCPD
0
1
1
0
0
1
0
1
/V
9–66, MSEL[n..0] represents
POR Delay
CCPGM
Standard
Standard
Fast
Fast
Fast
Fast
Fast
Fast
or GND. The
Standard (V)
Configuration
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
3.3, 3.0, 2.5
Voltage
IL
1.8
1.8
1.8
1.8
and V
(1)
9–9
IH
Related parts for EP2AGX190FF35C6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: