EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 536
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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2–46
Figure 2–26. FPGA Fabric-Receiver Interface Clocking for Non-Bonded Channel Configurations without Rate Matcher
Arria II Device Handbook Volume 2: Transceivers
Input Reference Clock
Input Reference Clock
Input Reference Clock
rx_datain[3]
rx_datain[2]
rx_datain[1]
rx_datain[0]
1
Receiver
Receiver
Receiver
Receiver
Channel
Channel
Channel
Channel
PMA
PMA
PMA
PMA
CDR
CDR
CDR
CDR
Non-Bonded Channel Configuration without Rate Matcher
In non-bonded channel configuration without the rate matcher, the Quartus II
software cannot determine if the incoming serial data in all channels have a 0 PPM
frequency difference. The Quartus II software automatically drives the read port of
the receiver phase compensation FIFO in each channel with the recovered clock
driven on the rx_clkout port of that channel. Use the rx_clkout signal from each
channel to latch its receiver data and status signals in the FPGA fabric.
This configuration uses one FPGA clock resource (global, regional, or both) per
channel for the rx_clkout signal.
Figure 2–26
channel configurations without rate matcher.
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Parallel Recovery Clock
Parallel Recovery Clock
Parallel Recovery Clock
Parallel Recovery Clock
shows the FPGA fabric-receiver interface clocking for non-bonded
Parallel Data
Parallel Data
Parallel Data
Parallel Data
/2
/2
/2
/2
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
rx_clkout[3]
rx_clkout[2]
rx_clkout[1]
rx_clkout[0]
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
FPGA Fabric
rx_coreclk[3]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
and Status
and Status
and Status
and Status
Channel 3
Channel 2
Channel 1
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
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