EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 455
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
December 2010 Altera Corporation
Figure 1–67
signal while transmitting the compliance pattern in 8-bit and 16-bit channel width
configurations, respectively.
Figure 1–67. Compliance Pattern Transmission Support, 8-Bit Wide Channel Configuration
Figure 1–68. Compliance Pattern Transmission Support, 16-Bit Wide Channel Configuration
Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit
RxStatus[2:0] signal. The PIPE interface block receives status signals from the
transceiver channel PCS and PMA blocks and drives the status on the 3-bit output
signal (pipestatus[2:0]) to the FPGA fabric. The encoding of the status signals on the
pipestatus[2:0] port is compliant with the PCIe specification and is listed in
Table
Table 1–18. Encoding of the Status Signals on the pipestatus[2:0] Port for Arria II Devices
pipestatus[2:0]
Note to
(1) The PIPE interface follows the priority listed in
pipestatus[2:0] port. Two or more error conditions; for example, 8B/10B decode error (code group violation),
rate match FIFO overflow or underflow, or receiver disparity error, can occur simultaneously. When this happens,
PIPE drives 3'b100 on the pipestatus[2:0] signal.
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
1–18.
tx_forcedispcompliance
Table
tx_forcedispcompliance[1:0]
1–18:
and
tx_datain[7:0]
tx_ctrldetect
Figure 1–68
tx_ctrldetect[1:0]
Elastic buffer (rate match FIFO) underflow
tx_datain[15:0]
Elastic buffer (rate match FIFO) overflow
One SKP symbol deleted
Received disparity error
One SKP symbol added
8B/10B decode error
K28.5
Received data OK
Receiver detected
BC
show the required level on the tx_forcedispcompliance
Description
/K28.5/D21.5/
D21.5
B5BC
B5
01
Table 1–18
K28.5
BC
/K28.5/D10.2/
BC4A
while encoding the receiver status on the
D10.2
4A
Arria II Device Handbook Volume 2: Transceivers
01
K28.5
/K28.5/D21.5/
BC
B5BC
Error Condition Priority
00
D21.5
B5
/K28.5/D10.2/
K28.5
BC
BC4A
N/A
N/A
5
6
1
2
3
4
D10.2
4A
(1)
1–69
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