TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 107

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

<BxW2:0>
(3) Wait control
(4) Bus width and wait control for an area other than CS0 to CS3
(5) Selecting 16-Mbyte area/specified address area
(6) Procedure for setting chip select/wait control
000
001
010
011
100
101
110
111
select/wait control register specify the number of waits that are to be inserted when the
corresponding memory area is accessed.
other than those listed in the table should not be made.
waits when memory locations, which are not in one of the four users specified address
areas (CS0 to CS3), are accessed. The BEXCS register settings are always enabled for
areas other than CS0 to CS3.
designates the 16-Mbyte area (000FE0H to 000FFFH, 003000H to FF7FFFH) as the
CS2 area. Setting B2CS<B2M> to 1 designates the address area specified by the start
address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if
B2CS<B2M> = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are).
order:
Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2>) of a chip
The following types of wait operation can be specified using these bits. Bit settings
A reset sets these bits to 000 (2 waits).
The chip select/wait control register BEXCS controls the bus width and number of
Setting B2CS<B2M> (Bit6 of the chip select/wait control register for CS2) to 0
A reset clears this bit to 0, specifying CS2 as 16-Mbyte address area.
When using the chip select/wait control function, set the registers in the following
a. Set the memory start address registers MSAR0 to MSAR3.
b. Set the memory address mask registers MAMR0 to MAMR3.
c. Set the chip select/wait control registers B0CS to B3CS.
master enable/disable status for
signal using one of these pins, set the corresponding bit in the port 6 function
register (P6FC) to 1.
Set the start addresses for CS0 to CS3.
Set the sizes of CS0 to CS3.
Set the chip select output waveform, data bus width, number of waits and
The CS0 to S3 pins can also function as pins P60 to P63. To output a chip select
Number of
(1 + N) waits
Reserved
Waits
2 waits
0 waits
3 waits
4 waits
8 waits
1 wait
Table 3.6.3 Wait Operation Settings
Inserts a wait of 2 states, irrespective of the
Inserts a wait of 1 state, irrespective of the
Samples the state of the
the
until the pin goes high.
Ends the bus cycle without a wait, regardless of the
Invalid setting
Inserts a wait of 3 states, irrespective of the
Inserts a wait of 4 states, irrespective of the
Inserts a wait of 8 states, irrespective of the
WAIT
91C820A-105
pin is low, the waits continue and the bus cycle is extended
CS0
to
WAIT
Wait Operation
CS3
pin after inserting a wait of one state. If
.
WAIT
WAIT
WAIT
WAIT
WAIT
pin state.
pin state.
pin state.
pin state.
pin state.
WAIT
pin state.
TMP91C820A
2008-02-20