TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 254

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(1) Frame frequency setting
(2) Frame invert adjustment function
setting mentioned before. However this f
number, frame period can be corrected by increasing f
cannot correct frame frequency higher than that of Table 3.14.8. If it is necessary to set
frame frequency higher or detailed, please refer to (3) “Timer out LCDCK”.
3.14.7.
If N is set in (LCDDVM) register while this function is set to enable in register
(LCDCTL) (<FRMON> “1”), D3BFR pin outputs the signal inverted polarity every
(D2BLP x N) timing.
frequency of DLEBCD pin after setting this function disable ((LCDCTL)<FRMON> =
0).
Note: Please make the value set to f
Note: Effects of this function have some differences as the LCD driver or LCD panel you
Basic frame period; DLEBCD signal, is made according to the resister f
The equation can calculate frame period.
Frame period = LCDCK/(D × f
Please select the value of f
(e.g.) In the case where frame period is set to 72.10 Hz by 240 coms.
Therefore, LCDCTL<FP8> = 1 and LCDFFP<FP7:0> = 2FH are setup.
This mode can prevent the deterioration of display (e.g., patches of display). (*Note)
If this function isn’t necessary, D3BFR pin outputs the signal inverted polarity every
And it is no change wave and timing for DLEBCD pin by LCDDVM setting.
use actually.
COM (common number) ≤ FR ≤ 1024
f
FP
= 240 (COM) + 63 = 303 = 12FH (by Table 3.14.8)
91C820A-252
FP
FP
[9:0] as the frame period you want to set in the Table
) [Hz]
FP
[9:0] into the following range.
FP
D: Constant for each common (Table 3.14.8)
f
LCDCK: Source clock of LCD
(Low clock is usually selected)
FP
[9:0] setting is generally equal to common
: Setting of f
FP
[9:0] with ease. This function
FP
[9:0] register
TMP91C820A
2008-02-20
FP
[9:0]