TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 45

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.4.1
General-purpose Interrupt Processing
operations. However, in the case of software interrupts and illegal instruction interrupts
generated by the CPU, the CPU skips steps a and c and executes only steps b, d and e.
bus width and 0 waits).
the main routine. RETI restores the contents of the program counter and the status
register from the stack and decrements the interrupt nesting counter INTNEST by 1.
however, can be enabled or disabled by a user program. A program can set the priority level
for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt
request.)
than the value set in the CPU interrupt mask register <IFF2:0>, the CPU will accept the
interrupt. The CPU interrupt mask register <IFF2:0> is then set to the value of the priority
level for the accepted interrupt plus 1.
interrupt begin currently processed, or if, during non-maskable interrupt processing, a
non-maskable interrupt request is generated from another source, the CPU suspends the
currently processing routine and accepts the later interrupt. Then, after the CPU finished
processing the later interrupt, the CPU returns to the interrupt it previously suspended
and resumes processing.
to e, the second interrupt is sampled immediately after execution of the first instruction for
its interrupt processing routine. Specifying DI as the start instruction disables maskable
interrupt nesting. (Note: In the 900 and 900/L, sampling is performed before execution of
the start instruction.)
interrupts.
FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area.
When the CPU accepts an interrupt, it usually performs the following sequence of
The above processing time is 18 states (1.00 µs at 36 MHz) as the best case (16-bit data
When the CPU completed the interrupt processing, use the RETI instruction to return to
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,
If an interrupt request is received for an interrupt with a priority level equal to or greater
If, during interrupt processing, an interrupt is generated with a higher level than the
If the CPU receives a request for another interrupt while performing processing steps a
A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all maskable
Table 3.4.1 shows the TMP91C820A interrupt vectors and micro DMA start vectors.
a.
b.
c.
d.
e.
The CPU reads the interrupt vector from the interrupt controller.
If there are simultaneous interrupts set to same level, the interrupt controller
generates an interrupt vector in accordance with the default priority and clears
the interrupt request.
(The default priority is already fixed for each interrupt: The smaller the vector
value, the higher the priority level.)
The CPU pushes the program counter (PC) and status register (SR) onto the top of
the stack (Pointed to by XSP).
The CPU sets the value of the CPU’s interrupt mask register <IFF2:0> to the
priority level for the accepted interrupt plus 1. However, if the priority level for
the accepted interrupt is 7, the register’s value is set to 7.
The CPU increments the interrupt nesting counter INTNEST by 1.
The CPU jumps to the address indicated by the data at address FFFF00H +
interrupt vector, and starts the interrupt processing routine.
91C820A-43
TMP91C820A
2008-02-20