TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 50

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

DMAM0 to
DMAM3
(Fixed)
000
( * ) For external 16-bit bus, 0 waits, word/4-byte transfer mode, transfer source/transfer destination
Note: n: Corresponding micro DMA channels 0 to 3.
addresses both have even-numbered values.
000
001
010
011
100
101
0
DMADn+/DMASn+: Post increment (Increments register value after transfer).
DMADn−/DMASn−: Post decrement (Decrements register value after transfer).
The I/Os in the table mean fixed address; memory means increment and decrement addresses.
Do not use undefined code, that is, codes other than those listed above for the transfer mode
register.
0
(4) Detailed description of the transfer mode register
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
0
Transfer Bytes
Byte transfer
Word transfer
4-byte transfer
Byte transfer
Word transfer
4-byte transfer
Byte transfer
Word transfer
4-byte transfer
Byte transfer
Word transfer
4-byte transfer
Byte transfer
Word transfer
4-byte transfer
Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
.....................For counting number of times interrupt is generated.
8 bits
Number of
Mode
Transfer destination address INC mode
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer destination address DEC mode
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address INC mode
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address DEC mode
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Fixed address mode
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
................................................. I/O to memory
................................................. I/O to memory
................................................. Memory to I/O
................................................. Memory to I/O
......................................................... I/O to I/O
Note: When setting a value in this register, write 0 to the upper
Mode Description
91C820A-48
three bits.
Execution States
Number of
12 sates
12 sates
12 sates
12 sates
12 sates
8 states
8 states
8 states
8 states
8 states
5 sates
(
*
)
Execution Time
at fc = 36 MHz
TMP91C820A
Minimum
444 ns
2008-02-20
444 ns
444 ns
444 ns
444 ns
667 ns
667 ns
667 ns
667 ns
667 ns
278 ns