TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 138

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

;Initial Setting
;CS0
;CS1
;CS2
;CS3
;CSX
;Port
to
to
set 1-wait setting. In the same way
waits,
memory size, need to set that logical address size: fitting to each local area. Actual physical
address is set by each area’s BANK register setting.
example isn’t used CSEX setting.
SDRAM condition.
Secondly, it shows example of initial setting at Figure 3.8.5.
Because
By CS/WAIT controller, each chip selection signal’s memory size, don’t set actual connect
CSEX setting of CS/WAIT controller is except above CS0 to CS3’s setting. This program
Finally pin condition is set. PORT60 to 65 set to
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDW
LD
LD
LD
LD
CS3
CS0
set 16-bit bus and 3 waits.
(MSAR0),00H
(MAMR0),FFH
(B0CS),89H
(MSAR1),40H
(MAMR1),FFH
(B1CS),83H
(MSAR2),C0H
(MAMR2),7FH
(B2CS),C3H
(MSAR3),80H
(MAMR3),7FH
(B3CS),85H
(BEXCS),00H
(P6FC),3FH
(P6FC2),02H
(PZCR),0707H
(PFFC),7FH
(SDACR),0ADH
(SDACR),06DH
(SDRCR),01H
connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it
Figure 3.8.5 Bank Operation S/W Example 1
; Logical address area: 000000H to 1FFFFFH
; Logical address size: 2 Mbytes
; Condition: 8 bits, 1 wait (8 Mbytes, SRAM)
; Logical address area: 400000H to 5FFFFFH
; Logical address size: 4 Mbytes
; Condition: 16 bits, 0 waits (16 Mbytes, SDRAM)
; Logical address area: C00000H to FFFFFFH
; Logical address size: 4 Mbytes
; Condition: 16 bits, 0 waits (16 Mbytes, MROM)
; Logical address area: 800000H to BFFFFFH
; Logical address size: 4 Mbytes
; Condition: 16 bits, 3 waits (64 Mbytes, MROM)
; Other: 16 bits, 2 waits (Don’t care)
;
;
;
; PF [6:0] = SDRAM control
; Add-MUX enable, 128-M select
; SDRAM setup time
; Add MUX enable, 128-M select
; Interval reflesh
CS0
HWR
CS1
91C820A-136
CS1
→
to
,
WR
CS3
set to 16-bit bus and 0 waits,
SDCS
,
, EA24, EA25: port 6 setting
RD
setting
CS0
,
CS1
,
CS2
,
CS2
CS3
set 16-bit bus and 0
, EA24, EA25 and
TMP91C820A
2008-02-20