TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 51

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.4.3
Interrupt Controller Operation
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
flip-flop), an interrupt priority setting register and a micro DMA start vector register. The
interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to
zero in the following cases: when reset occurs, when the CPU reads the channel vector of an
interrupt it has received, when the CPU receives a micro DMA request (When micro DMA
is set), when the micro DMA burst transfer is terminated, and when an instruction that
clears the interrupt for that channel is executed (by writing 0 to the clear bit in the
interrupt priority setting register).
priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). Six interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source. The priority of non-maskable interrupts (NMI
pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the
same level are generated at the same time, the default priority (The interrupt with the
lowest priority or, in other words, the interrupt with the lowest vector value) is used to
determine which interrupt request is accepted first.
interrupt request flag and thus whether an interrupt request for a given channel has
occurred.
simulateous interrupts and its vector address to the CPU. The CPU compares the priority
value <IFF2:0> et in the status register by the interrupt request signal with the priority
value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR<IFF2:0>. Interrupt request where the priority
value equals or is higher than the set value are accepted simultaneously during the
previous interrupt routine.
CPU restores the priority value saved in the stack before the interrupt was generated to
the CPU SR<IFF2:0>. The interrupt controller also has four registers used to store the
micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA
processing (See Table 3.4.1), enables the corresponding interrupt to be processed by micro
DMA processing. The values must be set in the micro DMA parameter register (e.g., DMAS
and DMAD) prior to the micro DMA processing.
The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the
For each of the 36 interrupt channels there is an interrupt request flag (Consisting of a
An interrupt priority can be set independently for each interrupt source by writing the
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the
The interrupt controller sends the interrupt request with the highest priority among the
When interrupt processing is completed (after execution of the RETI instruction), the
91C820A-49
TMP91C820A
2008-02-20