TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 34

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(2) How to release the HALT mode
release sources are determined by the combination between the states of interrupt
mask register <IFF2:0> and the HALT modes. The details for releasing the halt status
are shown in Table 3.3.4.
Released by requesting an interrupt
•
These halt states can be released by resetting or requesting an interrupt. The halt
Releasing by resetting
status. When the interrupt request level set before executing the halt instruction
exceeds the value of interrupt mask register,the interrupt due to the source is
processed after releasing the HALT mode, and CPU status executing an
instruction that follows the halt instruction. When the interrupt request level set
before executing the halt instruction is less than the value of the interrupt mask
register, releasing the HALT mode is not executed (in non-maskable interrupts,
interrupt processing is processed after releasing the HALT mode regardless of the
value of the mask register). However only for INT0 to INT3 and INTKEY and
INTRTC, INTALM0 to INTALM4, even if the interrupt request level set before
executing the halt instruction is less than the value of the interrupt mask register,
releasing the the HALT mode is executed. In this case, interrupt processing, and
CPU starts executing the instruction next to the HALT instruction, but the
interrupt request flag is held at 1.
(See Table 3.3.5) to set the operation of the oscillator to be stable.
state before the HALT instruction is executed. However the other settings
contents are initialized. (Releasing due to interrupts keeps the state before the
HALT instruction is executed.)
Note: Usually, interrupts can release all halt status. However, the interrupts (
The operating released from the HALT mode depends on the interrupt enabled
Releasing all halt status is executed by resetting.
When the stop mode is released by reset, it is necessry enough resetting time
When releasing the HALT mode by resetting, the internal RAM data keeps the
INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4) which can release the
HALT mode may not be able to do so if they are input during the period CPU is
shifting to the HALT mode (for about 5 clocks of f
mode (IDLE2 is not applicable to this case). (In this case, an interrupt request
is kept on hold internally.)
If another interrupt is generated after it has shifted to the HALT mode
completely, halt status can be released without difficulty. The priority of this
interrupt is compared with that of the interrupt kept on hold internally, and the
interrupt with higher priority is handled first followed by the other interrupt.
91C820A-32
FPH
) with IDLE1 or STOP
TMP91C820A
2008-02-20
NMI
,