TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 237

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.14.1
The number of picture
elements can be handled
Display memory data bus
width
LCD driver data bus width
Transfer rate
(at f
External
pins
FPH
= 36 [MHz])
Feature of LCDC of Each Mode
Each feature and operation of pin is as follows.
Data bus
(D7 to D0)
LCD data bus:
(LD7 to LD0)
Bus state
Address bus:
(A0)
Shift clock
pulse:
(D1BSCP)
Latch pulse:
(D2BLP)
Frame:
(D3BFR)
Cascade pulse:
(DLEBCD)
Display off:
(
DOFF
)
(Example: Toshiba made LCD driver T6C13B, T6B66A)
Table 3.14.1 Feature of LCDC of Each Mode
Common (Row):
Segment (Column): 128, 160, 240, 320,
16-bit fixed
8-bit fixed
Min 55 ns/1 word at SDRAM/BURST
Min 111 ns/1 word at SRAM
Not used
Data bus; connect to data bus of LCD
driver.
Not used
Not used
Shift clock pulses; connect with SCP pin of
segment driver. Driver latches data bus
value by falling edge of this pin.
Latch pulses output; connect with LP pin of
segment/common driver. Display data is
renewed in output register in LCD driver by
rising edge of this pin.
LCD frame output; connect with FR pin of
segment/common driver.
Cascade pulses output; connect with DIO1
pin of row driver. These pin outputs 1 shot
pulse by every D3BFR pin changes.
Display off output; connect with
display off and H means display on.
Shift Register Type LCD Driver
Control Mode
91C820A-235
128, 160, 200, 240,
320, 400, 480
400, 480, 560, 640
DSPOF
terminal of segment/common driver. L means
There is not a limitation
Depend on the setting of CS/WAIT
controller.
Data bus; connect to data bus of LCD
driver.
Not used
Bus state; connect with write enable pin of
segment/common driver.
Address 0; connect with D/I pin of
segment driver.
When A0 = 1 data bus value means
display data, when A0 = 0 data bus
means instruction data.
Chip enable for segment driver 1;
Connect with
Chip enable for segment driver 2;
Connect with
Chip enable for segment driver 3;
Connect with
Chip enable for common driver;
Connect with
RAM Built-in Type LCD Driver
Control Mode
CE
CE
CE
LE
pin of common driver.
pin of segment driver 1.
pin of segment driver 2.
pin of segment driver 3.
TMP91C820A
2008-02-20