TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 9

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

2.3
P00 to P07
D0 to D7
P10 to P17
D8 to D15
P20 to P27
A16 to A23
P30 to P37
A8 to A15
P40 o P47
A0 to A7
PZ0
PZ1
PZ2
PZ3
R/
P56
P60
P61
P62
P63
P64
EA24
P65
EA25
P66
P67
RD
WR
HWR
SRWR
WAIT
CS0
CS1
SDCS
CS2
CS2A
CS3
CS2B
CS2C
CS2D
SRLB
CS2E
SRUB
Pin Name
W
Pin Names and Functions
The names of the input/output pins and their functions are described below.
Number
of Pins
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Table 2.3.1 Pin Names and Functions (1/4)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 0: I/O port that allows I/O to be selected at the bit level
Data (Lower): Bits 0 to 7 of data bus
Port 1: I/O port that allows I/O to be selected at the bit level
(When used to the external 8-bit bus)
Data (Upper): Bits 8 to15 of data bus
Port 2: I/O port
Address: Bits 16 to 23 of address bus
Port 3: I/O port
Address: Bits 8 to 15 of address bus
Port 4: I/O port
Address: Bits 0 to 7 of address bus
Port Z0: Output port
Read: Strobe signal for reading external memory
Port Z1: Output port
Write: Strobe signal for writing data to pins D0 to D7
Port Z2: I/O port (with pull-up resistor)
High write: Strobe signal for writing data to pins D8 to D15
Port Z3: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle; 0 represents write cycle.
Write for SRAM: Strobe signal for writing data.
Port 56: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
Port 60: Output port
Chip select 0: Outputs 0 when address is within specified address area.
Port 61: Output port
Chip select 1: Outputs 0 when address is within specified address area
Chip select for SDRAM: Outputs 0 when address is within SDRAM address area
Port 62: Output port
Chip select 2: Outputs 0 when address is within specified address area
Expand chip select 2A: Outputs 0 when address is within specified address area
Port 63: Output port
Chip select 3: Outputs 0 when address is within specified address area
Port 64: Output port
Chip select 24: Outputs 0 when address is within specified address area
Expand chip select 2B: Outputs 0 when address is within specified address area
Port 65: Output port
Chip select 25: Outputs 0 when address is within specified address area
Expand chip select 2C: Outputs 0 when address is within specified address area
Port 66: Output port
Expand chip select 2D: Outputs 0 when address is within specified address area
Lower byte enable for SRAM: Outputs 0 when lower data is enable.
Port 67: Output port
Expand chip select 2E: Outputs 0 when address is within specified address area
Upper byte enable for SRAM: Outputs 0 when upper data is enable.
91C820A-7
Functions
TMP91C820A
2008-02-20