TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 130

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(Value to be compared)
Match with TA0REG
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PBCR
PBFC
TA01RUN
X: Don’t care, −: No change
Example: To output the following PWM waves on the TA1OUT pin at fc = 36 MHz:
Register buffer
overflow is detected when the TA0REG double buffer is enabled.
To achieve a 28.4 µs PWM cycle by setting φT1 to (2
Therefore n should be set to 7.
Since the low-level period is 16.0 µs when φT1 = 0.5 µs,
set the following value for TA0REG:
2
n
In this mode the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
TA0REG
overflow
28.4 µs ÷ (2
16.0 µs ÷ (2
MSB
← –
← 1
← 0
← X
← X
← X
← 1
7
* Clock state
6
X
1
1
X
–
–
X
Figure 3.7.18 Register Buffer Operation
Up counter = Q
5
X
1
0
X
–
–
X
3
3
16.0 µs
/fc)s ≈ 128 = 2
/fc)s ≈ 72 = 48H
4
X
0
0
X
–
–
X
28.4 µs
3
–
–
1
1
–
–
–
Q
Q
1
2
–
0
2
–
0
X
X
1
91C820A-128
1
1
–
0
0
1
1
1
–
LSB
n
0
0
1
0
X
–
–
1
System clock:
Clock gear:
Prescaler clock: f
Stop TMRA0 and clear it to 0.
Select 8-bit PWM mode (cycle: 2
input clock.
Write 48H.
Clear TA1FF to 0; enable the inversion and double buffer.
Set PB1 and the TA1OUT pin.
Start TMRA0 counting.
Shift into TA0REG
Up counter = Q
3
High frequency (fc)
1 (fc)
/fc)s (at fc = 36 MHz):
FPH
Q
2
TA0REG (Register buffer)
write
2
Q
3
7
) and select φT1 as the
TMP91C820A
2008-02-20
n