TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 48

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

D0 to D15
WR / HWR
A0 to A23
States 1 to 3: Instruction fetch cycle (Gets next address code).
States 4 to 5
State 6
States 7 to 8
Note 1: If the source address area is an 8-bit bus, it is incremented by two states.
Note 2: If the destination address area is an 8-bit bus, it is incremented by two states.
RD
X1
:
Dummy cycle (The address bus remains unchanged from state 5).
If the source address area is a 16-bit bus and the address starts from an odd number, it is
incremented by two states.
If the destination address area is a 16-bit bus and the address starts from an odd number, it is
incremented by two states.
One state
DM1
:
:
32-bit control register, this register can only effectively output 24-bit addresses.
Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not
valid).
transfer, and 4-byte transfer. After a transfer in any mode, the transfer
source/destination addresses are incremented, decremented, or remain unchanged.
from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) “Detailed description of
the transfer mode register”. As the transfer counter is a 16-bit counter, micro DMA
processing can be set for up to 65536 times per interrupt source. (The micro DMA
processing count is maximized when the transfer counter initial value is set to 0000H.)
start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 32
interrupts.
address INC mode (except for counter mode, the same as for other modes).
source/transfer destination addresses both even-numberd values).
If three or more instruction codes are inserted in the instruction queue buffer, this cycle
becomes a dummy cycle.
Micro DMA read cycle.
Micro DMA write cycle.
While the register for setting the transfer source/transfer destination addresses is a
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word)
This simplifies the transfer of data from I/O to memory, from memory to I/O, and
Micro DMA processing can be started by the 31 interrupts shown in the micro DMA
Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer
DM2
DM3
Figure 3.4.2 Timing for Micro DMA Cycle
DM4
Transfer source address
(Note 1)
DM5
Input
91C820A-46
DM6
DM7
Transfer destination
(Note 2)
address
Output
DM8
TMP91C820A
2008-02-20