TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 35

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

♦ : After clearing the HALT mode, CPU starts interrupt processing.
○
× : It can not be used to release the HALT mode .
− : The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
* 1: Releasing the HALT mode is executed after passing the warm-up time.
Note:
: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT
Status of Received Interrupt
instruction.
level. There is not this combination type.
(Example releasing IDLE1 mode)
NMI
INTWDT
INT0 to INT3 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3, INTTB00 to
INTTB01
INTRX0 to INTRX2, TX0 to TX2
INTSS0 to INTSS2
INTAD
INTKEY
INTRTC
INTSBI
INTLCD
RESET
When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled
status, hold level H until starting interrupt processing. If level L is set before holding level L,
interrupt processing is correctly started.
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
HALT mode
Address
8200H
8203H
8206H
8209H
820BH
820EH
820FH
INT0
Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation
LD
LD
LD
EI
LD
HALT
LD
(PBFC), 08H
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 88H
XX, XX
(Interrupt level) ≥ (Interrupt mask)
IDLE2
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Interrupt Enabled
91C820A-33
; Sets PB3 to INT0.
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets HALT mode to IDLE1 mode.
; Halts CPU.
IDLE1
♦
♦
♦
♦
♦
×
×
×
×
×
×
×
STOP
♦
♦
♦
×
×
×
×
×
×
×
×
×
Initialize LSI.
* 1
* 1
* 1
INT0 interrupt routine
(Interrupt level) < (Interrupt mask)
IDLE2
RETI
○
○
○
○
−
−
×
×
×
×
×
×
Interrupt Disabled
IDLE1
TMP91C820A
○
○
○
○
−
−
×
×
×
×
×
×
2008-02-20
STOP
○
○
−
−
×
×
×
×
×
×
×
×
* 1
* 1