TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 280

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

SDACR
(04F0H)
SDRCR
(04F1H)
3.16.1
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Control Registers
operation of SDRAMC.
become Entry by writing “1” to it. If wrote “0” to SDRCR<SFRC>, Self refresh mode become
Exit.
Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the
Self refresh operation is controlled by setting SDRCR<SFRC>, and self-refresh mode
Auto
initialize
0: Disable
1: Enable
Self
refresh
0: Exit
1: Entry
SDINI
SFRC
R/W
R/W
7
7
0
0
Write
recovery
0: 1 clock
1: 2 clock
Auto refresh interval
000: 78 states
001: 97 states
010:124 states
011:156 states
Figure 3.16.1 SDRAMC Control Registers
SWRC
SRS2
R/W
6
0
6
0
SDRAM Refresh Control Register
SDRAM Access Control Register
Always write “10”.
SRS1
R/W
R/W
5
5
−
1
0
91C820A-278
100: 195 states
101: 210 states
110: 249 states
111: 312 states
SRS0
R/W
4
4
−
0
0
Address
multiplex
0: Disable
1: Enable
Always
write “0”.
SMUXE
R/W
R/W
3
3
0
−
0
SDRAM select
00: 16 Mbits 10: 128 Mbits
01: 64 Mbits 11: Reserved
SMUXW1 SMUXW0
2
2
0
R/W
1
1
0
TMP91C820A
SDRAM
controller
0: Disable
1: Enable
Auto
refresh
0: Disable
1: Enable
SMAC
SRC
R/W
R/W
2008-02-20
0
0
0
0