TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 92

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.5.14
Port C (PC0 to PC5)
input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the
output latch register to 1.
as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a 1 to the
corresponding bit of the port C function register (PCFC).
ports.
(1) Port C0, C3 (TXD0/TXD1)
Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function
Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input
TXD0, TXD1
channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by
setting the register PC<PC0, 3>.
the register PCODE<ODEPC0, 3>.
As well as functioning as I/O port pins, port C0 and C3 can also function as serial
And ports C0 to C3 have a programmable open-drain function, which can be control
PC write
Output latch
S
Direction control
Function control
PCFC write
(on bit basis)
PCCR write
(on bit basis)
PC read
Reset
Logical invert
Figure 3.5.36 Port C0 and Port C3
A
B
Selector
Selector
S
S
91C820A-90
B
A
PCODE
<ODEPC0, 3>
Open-drain
possible:
PC0 (TXD0)
PC3 (TXD1)
TMP91C820A
2008-02-20