TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 298

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(4) Capture registers (TB0CP0H/L)
(5) Capture input control
(6) Comparators (CP0 and CP1)
(7) Timer flip-flops (TB0FF0)
data load instruction or two 1-byte data load instructions. The least significant byte is
read first, followed by the most significant byte.
Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the up counter is
loaded into capture register TB0CP0. It is necessary to keep the prescaler in RUN
mode (e.g., TB0RUN<TB0PRUN> must be held at a value of 1).
with the value set in TB0RG0 or TB0RG1 respectively, in order to detect a match. If a
match is detected, the comparator generates an interrupt (INTTB00 or INTTB01
respectively).
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C0T1, TB0E1T1, TB0E0T1>.
<TB0FF0C1:0> or <TB0FF1C1:0>, TB0FF0 will be inverted. If 01 is written to the
capture registers, the value of TB0FF0 will be set to 1. If 10 is written to the capture
registers, the value of TB0FF0 will be set to 0.
shared with PB6). Timer output should be specified using the port B function register.
Note: As described above, whenever 0 is written to TB0MOD<TB0CP0I>, the current
These 16-bit registers are used to latch the values in the up counters.
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
The addresses of the capture registers are as follows:
This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0.
The value in the up-counter can be loaded into a capture register by software.
CP0 and CP1 are 16-bit comparators which compare the value in the up counter UC0
These flip-flops are inverted by the match detect signals from the comparators and
After a reset the value of TB0FF0 is undefined. If 00 is written to TB0FFCR
The values of TB0FF0 can be output via the timer output pins TB0OUT0 (which is
The capture registers are read-only registers and thus cannot be written to.
TMRB0
value in the up counter is loaded into capture register TB0CP0. However, note that
the current value in the up counter is also loaded into capture register TB0CP0
when 1 is written to TB0MOD<TB0CP0I> while this bit is holding 0.
Write to TB0MOD
register
TB0MOD
<TB0CP0I>
CAPTURE
operation
(TB0CP0H)
MS 8 bits
00018DH
TB0CP0
91C820A-296
(TB0CP0L)
00018CH
LS 8 bits
Capture
“0” WR
Capture
“0” WR
Notice
Capture
“1” WR
“1” WR
No capture
TMP91C820A
2008-02-20