TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 136

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TMP91xy20AFG

Manufacturer Part Number
TMP91xy20AFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy20AFG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M
Rom Combinations
8
Ram Combinations
8
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
77
Power Supply Voltage(v)
3.0 to 3.6
LOCAL0
(0350H)
LOCAL1
(0351H)
LOCAL2
(0352H)
LOCAL3
(0353H)
3.8.2
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Explanation of SFR
setting bank.
controller need to be set. When CPU outputs logical address of the LOCAL area, MMU
outputs physical address to the outside address bus pin according to value of bank setting
register. Access of external memory becomes possible therefore.
There are 4 registers; LOCAL0 to LOCAL3. Each register is for enabling bank and
Setup LOCAL registers in common area. And, a combination pin and the CS/WAIT
BANK for
LOCAL0
0: Disable
1: Enable
BANK for
LOCAL1
0: Disable
1: Enable
BANK for
LOCAL2
0: Disable
1: Enable
BANK for
LOCAL3
0: Disable
1: Enable
R/W
R/W
R/W
R/W
L0E
L1E
L2E
L3E
0
0
0
0
7
7
7
7
Figure 3.8.3 Register for LOCAL0 to LOCAL3
6
6
6
6
5
5
5
5
91C820A-134
LOCAL0 Register
LOCAL1 Register
LOCAL2 Register
LOCAL3 Register
01000 to 01011:
00000 to 00011:
00100 to 00111:
L3EA26
R/W
0
4
4
4
4
11000 to 11111: Set prohibition
L3EA25
R/W
CS2D
CS2B
CS2C
0
3
3
3
3
Setting BANK number for LOCAL0
Setting BANK number for LOCAL1
Setting BANK number for LOCAL2
L0EA22
L1EA23
L2EA23
L3EA24
01100 to 01111:
10000 to 10011:
10100 to 10111:
R/W
Do not set “000” because of
Do not set “001” because of
Do not set “111” because of
0
0
0
0
2
2
2
2
common area
common area
common area
L0EA21
L1EA22
L2EA22
L3EA23
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
CS2E
CS2F
CS2G
L0EA20
L1EA21
L2EA21
L3EA22
TMP91C820A
R/W
0
0
0
0
0
0
0
0
2008-02-20

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