TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 113

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.7.2
xxx: Don’t care
<SYSCK>
Selection
System
Clock
1 (fs)
0 (fc)
Operation of Each Circuit
(1) Prescaler
(2) Up counters (UC0 and UC1)
Prescaler Clock
fc/16 and is selected using the prescaler clock selection register SYSCR0<PRCK1:0>.
timer control register. Setting <TA01PRUN> to 1 starts the count; setting
<TA01PRUN> to 0 clears the prescaler to 0 and stops operation. Table 3.7.2 shows the
various prescaler output clock resolutions.
specified by TA01MOD.
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD<TA0CLK1:0><TA1CLK1:0>.
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up counters
and to control their count. A reset clears both up counters, stopping the timers.
<PRCK1:0>
(fc/16 CLOCK)
A 9-bit prescaler generates the input clock to TMRA01.
The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either f
The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the
These are 8-bit binary counters which count up the input clock pulses for the clock
The input clock for UC0 is selectable and can be either the external clock input via
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
For each interval timer the timer operation control register bits TA01RUN
Selection
(f
FPH
00
10
)
Table 3.7.2 Prescaler Output Clock Resolution
<GEAR2:0>
XXX
000 (fc)
001 (fc/2)
010 (fc/4)
011 (fc/8)
100 (fc/16)
XXX
Gear Value
91C820A-111
2
2
2
2
2
2
2
3
3
4
5
6
7
7
/fs (244 µ s)
/fc (0.2 µ s)
/fc (0.4 µ s)
/fc (0.9 µ s)
/fc (1.8 µ s)
/fc (3.6 µ s)
/fc (3.6 µ s)
φT1
Prescaler Output Clock Resolution
2
2
2
2
2
2
2
9
9
5
5
6
7
8
/fc (14.2 µ s) 2
/fc (14.2 µ s) 2
/fs (977 µ s) 2
/fc (0.9 µ s) 2
/fc (1.8 µ s) 2
/fc (3.6 µ s) 2
/fc (7.1 µ s) 2
φT4
7
7
8
9
10
11
11
/fs (3.9 ms)
/fc (3.6 µ s)
/fc (7.1 µ s)
/fc (14.2 µ s)
/fc (28.4 µ s)
/fc (56.9 µ s)
/fc (56.9 µ s)
at fc = 36 MHz, fs = 32.768 kHz
φT16
2
2
2
2
2
2
2
11
11
12
13
14
15
15
/fs (62.5 ms)
/fc (56.9 µ s)
/fc (113.8 µ s)
/fc (227.6 µ s)
/fc (455.1 µ s)
/fc (910.2 µ s)
/fc (910.2 µ s)
φT256
TMP91C820A
2008-02-20
FPH
or