TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 169

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TMP91xy20AFG

Manufacturer Part Number
TMP91xy20AFG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy20AFG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M
Rom Combinations
8
Ram Combinations
8
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
1
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
77
Power Supply Voltage(v)
3.0 to 3.6
IRX1C
(INTRX1
interrupt request)
SCLK1 output
(<SCLKS>=0
Rising edge mode)
SCLK1 output
(<SCLKS>=1
Fallingf edge mode)
RXD1
Note: The system must be put in the receive enable state (SCMOD0<RXE> = 1) before data can be
(INTRX1 )
IRX1C
SCLK1 input
(<SCLKS> = 0:
Rising edge mode)
SCLK1 input
(<SCLKS> = 1:
Falling edge mode)
RXD1
received.
Figure 3.9.27 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
Figure 3.9.28 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
b.
Receiving
the data is shifted to receiving buffer 1. This starts when the receive interrupt flag
INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are
received, the data will be transferred to receiving buffer 2 (SC0BUF according to
the timing shown below) and INTES0<IRX0C> will be set to generate INTRX0
interrupt.
input becomes active after the receive interrupt flag INTES0<IRX0C> is cleared
by reading the received data. When 8-bit data is received, the data will be shifted
to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0
<IRX0C> will be set again to be generate INTRX0 interrupt.
In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and
The outputting for the first SCLK0 starts by setting SC0MOD0<RXE> to 1.
In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK
Bit0
Bit0
91C820A-167
(Channel 0)
(Channel 0)
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91C820A
2008-02-20

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