TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 137

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

TMP91C820A
Control signals
* In case of 16-bit bus memory
ROM: MROM, 16 Mbyte, data ROM: MROM, 64 Mbyte, data RAM: SRAM, 8 Mbyte, 8-bit bus,
display RAM: SDRAM, 16 Mbytes.
and 8-bit bus case, direct connection address bus from TMP91C820A.
chip select signal, RAM:
of this example, as data MROM is 64 Mbyte, this MROM connect to EA24 and EA25.
program ROM. It can set free setting except program ROM.
TMP91C820A
At Figure 3.8.4, it shows example of connection TMP91C820A and some memories: program
In case of 16-bit bus memory connection, it need to shift 1-bit address bus from TMP91C820A
In that figure, logical address and physical address are shown. And each memory allot each
Initial condition after reset, because TMP91C820A access from CS2 area, CS2 area allots to
D [0:15]
A16
A0
A1
A2
RD
SDCS
SDLDQM, SDUDQM
:
:
, (
SDCLK, SDCKE,
WR
EA24, EA25
,
SDRAS
Address
SDWE
Data
CS0
CS1
,
Control signals
D [0:15]
Open
A0
A1
A15
CS2
CS3
HWR
Memory
CS0
Figure 3.8.4 H/W Setting Example
,
: SRAM)
SDCAS
, SDRAM:
91C820A-135
CS1
, program MROM:
16 Mbytes
16 Mbytes
64 Mbytes
8 Mbytes
* In case of 8-bit bus memory
TMP91C820A
SDRAM
MROM
MROM
SRAM
16 bits
16 bits
16 bits
8 bits
Control signals
D [0:7]
Data/stack SRAM
000000H to 1FFFFFH (Logical)
000000H to 7FFFFFH (Physical)
Display SDRAM
000000H to FFFFFFH (Physical)
Program ROM
C00000H to FFFFFFH (Logical)
000000H to FFFFFFH (Physical)
Data ROM
800000H to BFFFFFH (Logical)
0000000H to 3FFFFFFH (Physical)
CS3
CS1
CS2
CS3
A0
A1
A2
A7
400000H to 7FFFFFH (Logical)
CS2
, data MROM:
:
:
Control signals
D [0:7]
A0
A1
A2
A7
Memory
TMP91C820A
2008-02-20
CS3
in case