RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 100

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

5.0 Electrical and Mechanical Specifications
5.6 Microcomputer Interface Timing
Table 5-14. Microcomputer Interface Switching Characteristics
5-12
NOTE(S):
(1) Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola mode.
(2) When writing an interrupt mask or status register.
(3) Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola mode.
(4) Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after the
(5) When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x71–0x7B] and the
(6) When performing an indirect read from RAM-based locations using a read select register [even addresses: 0x70–0x7A] and the
(7) The timing listed is for the synchronous mode of the MCI, which is power-on default. It can also be set to asynchronous mode
Symbol
49
50
51
52
53
54
55
56
57
58
59
60
61
62
specified time. This parameter may extend the overall read access time from internal register locations under high bus
speed/low symbol rate conditions.
Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated by a Write
Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access time to RAM-based
locations under normal bus speed/symbol rate conditions.
Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling-edge, is
prohibited for the specified time. Data is available for reading from the Access Data Register after the specified time. This
parameter will extend the overall read access time from RAM-based locations under normal bus speed/symbol rate conditions.
Direct writes to the Access Data Register are as specified for internal registers.
by setting bit 0 of the reserved9 register (address 0x0F) to a 1. In this case, the minimum timing changes to 40 ns for symbol
39, and 50 ns for symbols 40 and 50. Synchronous mode is preferred because it reduces switching noise. To switch to
asynchronous mode, the Write Strobe pulse-width (symbol 39) should meet the synchronous mode timing requirements for a
symbol rate of 640 kbps (74 nx), which is the power-on default.
Data out enable (Low Z) after Read Strobe falling edge
Data out valid after Read Strobe low
Data out hold after Read Strobe rising edge
Data out disable (High Z) after Read Strobe high
IRQ hold after Write Strobe rising edge
IRQ delay after Write Strobe high
Internal register delay after Write Strobe high
Internal RAM delay after Write Strobe high
Access data register delay after Write Strobe high
READY low after Write Strobe low
READY rising edge after Write Strobe high
READY low after Read Strobe low
READY rising edge after Read Strobe high
Data out valid after READY low
Parameter
(2,3)
(1)
(3)
(1, 7)
(2,3)
Preliminary Information
(1)
(3,5)
(3)
(1)
(3,4)
Conexant
(1)
(3,6)
(1)
Minimum
Single-Chip SDSL/HDSL Transceiver
—
—
—
—
—
—
—
2
2
5
0
0
0
0
T
T
QCLK
QCLK
Maximum
T
T
T
2 × T
2 × T
QCLK
QCLK
QCLK
÷ 32 + 25
÷ 32 + 20
—
—
25
—
50
50
10
QCLK
QCLK
÷ 32
÷ 32
÷ 32
N8973DSD
RS8973
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns