RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 65

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
switch_cap_pole
gain[2:0]
clk_freq[9,8]
phase_detector_
gain[1,0]
freeze_pll
pll_gain[1,0]
N8973DSD
0x22—PLL Modes Register (pll_modes)
clk_freq[9]
7
clk_freq[8]
Switch Cap Pole Control—Read/write control bit, specifies the pulse shaping filter
characteristics. When switch_cap_pole is set, it enables output pulse shape conforming to
ETSI specifications for 2320 kbps operation. When reset, it enables output pulse shape for
other data rates.
Gain Control—Read/write binary field that specifies the gain of the VGA.
Clock Frequency Select—See description for
(clock_freq_select).
Phase Detector Gain—Read/write binary field that specifies one of three gain settings for the
timing-recovery phase detector function.
Freeze PLL—Read/write control bit. When set, this bit zeros the proportional term of the loop
compensation filter and disables accumulator updates, causing the PLL to hold its current
frequency. When this bit is cleared, proportional term effects and accumulator updates are
enabled, allowing the PLL to track the phase of the incoming data.
PLL Gain—Read/write binary field that specifies the gain (proportional and integral
coefficients) of the loop compensation filter.
6
gain[2:0]
phase_detector_gain[1,0]
pll_gain[1:0]
000
001
010
011
100
101
110
111
—
5
00
01
10
11
00
01
10
11
phase_detector_
Preliminary Information
VGA Gain
gain[1]
12 dB
15 dB
15 dB
15 dB
0 dB
3 dB
6 dB
9 dB
4
Conexant
Proportional Coefficients
phase_detector_
Normalized
gain[0]
Normalized Gain
3
16
64
0x20—Clock Frequency Select Register
1
4
Reserved
1
2
4
freeze_pll
2
Integral Coefficients
pll_gain[1]
Normalized
3.3 Register Description
1
4096
256
32
1
3.0 Registers
pll_gain[0]
0
3-19