RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 22

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

1.0 System Overview
1.2 Pin Descriptions
Table 1-2. Hardware Signal Definitions (4 of 4)
1-10
TDI
TMS
TDO
TCK
SMON
DTEST[1:4]
DTEST[5, 6]
ATEST[1,2]
VDD1
VDD2
VPLL
PGND
DGND
VAA
AGND
Pin Label
JTAG Test Data
Input
JTAG Test Mode
Select
JTAG Test Data
Output
JTAG Test Clock
Input
Serial Monitor
Digital Tests 1–4
Digital Test 5, 6
Analog Test 1, 2
Core Logic Power
Supply
I/O Buffer Power
Supply
PLL Power Supply
PLL Ground
Digital Ground
Analog Power
Supply
Analog Ground
Signal Name
I/O
IA
O
O
–
–
–
–
–
–
–
I
I
I
I
I
Test and Diagnostic Interface
JTAG test data input per IEEE Std 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of TCK.
TDI can be left unconnected if it is not being used because it is pulled up
internally.
JTAG test mode select input per IEEE Std 1149.1-1990. Internally pulled-up
input signal used to control the test-logic state machine. Sampled on the rising
edge of TCK. TMS can be left unconnected if it is not being used because it is
pulled up internally.
JTAG test data output per IEEE Std 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic. Updated on
the falling edge of TCK.
JTAG test clock input per IEEE Std 1149.1-1990. Used for all test interface and
internal test logic operations. If unused, TCK should be pulled low.
Serial data output used for real-time monitoring of internal signal-path registers.
The source register is selected through the Serial Monitor Source Select
Register [serial_monitor_source; 0x01]. The 16-bit words are shifted out, LSB
first, at 16 times the symbol rate. The rising edge of QCLK defines the start LSB
of each word. The output is updated on the rising edge of an internal clock
running at 16 times QCLK.
Active-high test inputs used by Conexant to enable internal test modes. These
inputs should be tied to digital ground (DGND).
Active-low test inputs used by Conexant to enable internal test modes. These
inputs should be tied to the I/O buffer power supply (VDD2).
Analog test inputs used by Conexant for internal test modes. These inputs
should be left floating (No Connect, NC).
Dedicated supply pins powering the digital core logic functions.
Connect to 3.3 V.
Dedicated supply pins powering the digital I/O buffers. Connect to 5 V.
Dedicated supply pins powering the PLL and the crystal amplifier.
Connect to 5 V.
Dedicated ground pins for the PLL and the crystal amplifier. Must be held at the
same potential as DGND and AGND.
Dedicated ground pins for the digital circuitry. Must be held at same potential as
AGND and PGND.
Dedicated supply pins powering the analog circuitry.
Dedicated ground pins for the analog circuitry. Must be held at the same
potential as DGND and PGND.
Preliminary Information
Power and Ground
Conexant
Definition
Single-Chip SDSL/HDSL Transceiver
N8973DSD
RS8973