RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 96

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

5.0 Electrical and Mechanical Specifications
5.5 Channel Unit Interface Timing
Table 5-9. Channel Unit Interface Timing Requirements, Parallel Slave Mode
Table 5-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode
Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode
5-8
NOTE(S):
(1) TBCLK and RBCLK must be frequency-locked to QCLK, though they may have independent phase relationships to QCLK and to
(2) TBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes 0x06].
NOTE(S):
(1) RBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes; 0x06].
Symbol
Symbol
18
19
20
21
22
one another.
23
24
TBCLK, RBCLK Period
TBCLK
TBCLK
TQ[1,0] Setup prior to TBCLK Active Edge
TQ[1,0] Hold after TBCLK High/Low
RQ[1,0] hold after RBCLK active edge
RQ[1,0] delay after RBCLK high/low
,
,
RBCLK Pulse-Width High
RBCLK Pulse-Width Low
RQ[1:0]
RBCLK
TQ[1:0]
TBCLK
(1)
Parameter
Parameter
(2)
(1)
(1)
19
Preliminary Information
(2)
Conexant
19
21
18
23
18
24
20
22
20
Single-Chip SDSL/HDSL Transceiver
Minimum
Minimum
T
T
QCLK
QCLK
T
QCLK
25
25
—
0
4
4
Maximum
Maximum
T
100
QCLK
—
—
—
—
—
N8973DSD
RS8973
Units
Units
—
—
—
ns
ns
ns
ns