RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 35

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
N8973DSD
2.2.7.4 Scrambler
Module
The scrambler can operate as either a scrambler or as a descrambler. The
scrambler block is used during the scrambled-1s part of the start-up sequence.
This provides an error-free signal for equalizer adaptation. This scrambler is
essentially a 23-bit-long Linear Feedback Shift Register (LFSR). The feedback
point depends on whether the transceiver is being used in a central-office or
remote-terminal application.
output. The symbol is converted to a bit stream as shown in
two-level case.
Table 2-4. Two-Level Symbol-to-Bit Conversion
four-level case.
Table 2-5. Four-Level Symbol-to-Bit Conversion
case it is clocked once per symbol, and in the four-level case it is clocked twice
per symbol.
source. Once locked, it is then able to replicate the far-end input sequence when
its input is held at all 1s. The locking sequence is controlled internally, initiated
through the MCI by setting the lfsr_lock bit of the detector_modes register. The
locking sequence consists of the following four steps:
microcomputer.
When the LFSR is operating as a descrambler, the input source is the detector
The symbol is converted to a bit stream as shown in
The LFSR operates in the same way in both cases, except that in the two-level
When operating as a scrambler, the LFSR must first be locked to the far-end
1.
2.
3.
4.
The sequence continues until the lfsr_lock control bit is cleared by the
Operate the LFSR as a descrambler for 23 bits.
Operate the LFSR as a scrambler for 127 bits. The sync detector is active
during this period.
Go to Step 1 if synchronization was not achieved; otherwise, continue to
Step 4.
Send an interrupt to the microcomputer if unmasked, indicating successful
locking, and continue operating as a scrambler.
Input Symbol
– 3
– 1
+ 1
+ 3
Preliminary Information
Input Symbol
– 3
+ 3
Conexant
First Output Bit
(Sign)
0
0
1
1
2.0 Functional Description
Table 2-5
Output Bit
Second Output Bit
Table 2-4
0
1
(Magnitude)
2.2 Receive Section
for the
0
1
1
0
for the
2-11