RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 79

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimal.
When written, this register causes the lowest-order 16 bits of the Access Data Register [access_data_byte[3:0];
0x7C–0x7F] to be subsequently written to the selected equalizer register file location within 2 symbol periods.
Does not affect the value of the access data register. An address map of the shared register file, as defined by the
factory-delivered microcode, is displayed in
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes the selected 32-bit location of the equalizer microprogram store to be
subsequently loaded into the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within 2 symbol
periods. Does not affect the value of the microprogram store location. No other data access should occur
between the time the Read Tap Select Register is written and the time the Access Data Register is read, or the
data may be corrupted.
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimal.
When written, this register causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F]
to be subsequently written to the selected equalizer microprogram store location within 2 symbol periods. Does
not affect the value of the access data register. A factory-developed equalizer microcode is included with the
no-fee licensed HDSL transceiver software available from Conexant.
A 4-byte read/write register that stores filter coefficient, equalizer register file, and equalizer microprogram
store contents during indirect accesses to these RAM-based locations. Writes to addresses 0x70 through 0x7B,
and uses the contents of this shared register as specified in each of the individual register descriptions.
N8973DSD
0x79—Equalizer Write Select Register (eq_add_write)
0x7A—Equalizer Microcode Read Select Register (eq_microcode_add_read)
0x7B—Equalizer Microcode Write Select Register (eq_microcode_add_write)
0x7C–0x7F—Access Data Register (access_data_byte3:0)
—
—
—
7
7
7
—
—
—
6
6
6
D[5]
D[5]
D[5]
5
5
5
Preliminary Information
Table 3-2, Address Map of Shared Register
D[4]
D[4]
D[4]
4
4
4
Conexant
D[3]
D[3]
D[3]
3
3
3
D[2]
D[2]
D[2]
2
2
2
Fill.
D[1]
D[1]
D[1]
3.3 Register Description
1
1
1
3.0 Registers
D[0]
D[0]
D[0]
0
0
0
3-33