RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 64

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
clk_freq[7:0]
cont_time[1,0]
loop_back[1,0]
3-18
0x20—Clock Frequency Select Register (clock_freq_select)
0x21—ADC Control Register (adc_control)
cont_time[1]
clk_freq[7]
7
7
cont_time[0]
clk_freq[6]
Read/write binary field, which along with clk_freq[9,8] of the PLL Modes Register (0x22),
specifies the data rate used by the clock synthesizer to generate the appropriate internal clock.
1280 kbps.
Continuous Time Control—Read/write binary field that controls the cut-off frequency of the
analog RC reconstruction filter, according to the data rates.
The “00” setting of the continuous_time control bits enables an output pulse shape that
conforms to the ETSI HDSL specifications at 1168 kbps.
specifications at 784 kbps.
specifications at 2320 kbps.
Loopback Control—Read/write binary field that specifies if loopback is enabled, and the type
of loopback that is enabled. During transmitting loopback, the differential receiver inputs
(RXP, RXN) are disabled. The loopback path is intended to go from the transmitter outputs
(TXP, TXN) through the external hybrid circuit and back into the differential receiver balance
inputs (RXBP, RXBN). During silent loopback, the transmitter is turned off. The output of the
pulse-shaping filter in the transmit section is internally connected to the input of the ADC in
the receive section.
clk_freq = 18 to 290
data rate = clk_freq × 8 kbps (144 kbps to 2320 kbps)
The power-on default is clk_freq = 0 which selects the internal clock corresponding to
The “01” setting enables an output pulse shape that conforms to the ANSI and ETSI HDSL
The “10” setting enables an output pulse shape that conforms to the ETSI HDSL
6
6
loop_back[1]
cont_time[1,0]
loop_back[1,0]
clk_freq[5]
5
5
00
01
10
11
00
01
10
11
loop_back[0]
Preliminary Information
clk_freq[4]
4
4
Conexant
800 to 1200 kbps
Less than 800 kbps
Above 1200 kbps
Reserved
Data Rate Range
Function
Normal Operation (Loopback Disabled)
Hybrid Inputs Disabled (RXBP, RXBN)
Transmitting Loopback
Silent Loopback
switch_cap_pole
clk_freq[3]
3
3
clk_freq[2]
gain[2]
Single-Chip SDSL/HDSL Transceiver
2
2
clk_freq[1]
gain[1]
1
1
N8973DSD
clk_freq[0]
gain[0]
RS8973
0
0