RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 43

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
2.5.3 Interrupt Request
N8973DSD
2.5.2.1 RAM Access
2.5.2.2 Multiplexed
2.5.2.3 Separated
Address/Data Bus
Registers
Data Bus
Address/
The internal RAM of the scratch pad, LEC, NEC, DFE, equalizer, and microcode
are accessed indirectly. They all share a common data register which is used for
both read and write operations: Access Data Register [access_data_byte[3:0];
[0x7C–0x7F]. Each RAM has an individual read select and write select register.
Writes to these registers specify the location to access and trigger the actual RAM
read or write.
the corresponding read tap select register. Two symbol periods afterward, the
individual bytes of that location are available for reading from the Access Data
Register.
Register. The address of the affected RAM location is then written to the
corresponding write tap select register. When writing the same value to multiple
locations, it is not necessary to rewrite the Access Data Register.
operations are performed synchronous to the symbol clock. This limits access to
the internal RAM to one every other cycle.
freeze adaptation so that all values correspond to the same state.
The timing for a read or write cycle is stated explicitly in
and Mechanical
microcomputer places an address on the address-data bus, which is then latched
on the falling edge of ALE. Data are placed on the address-data bus after CS and
RD, or CS and DS go low. The read cycle is completed with the rising edge of CS
or RD or DS.
edge of ALE. The microcomputer places data on the address-data bus after CS,
and WR or CS and DS go low. Motorola MCI has R/W falling edge preceding the
falling edge of CS and DS. The rising edge of R/W occurs after the rising edge of
CS and DS. Data are latched from the address-data bus on the rising edge of CS
or WR or DS.
The timing for a read or write cycle using the separated address and data buses is
essentially the same as over the multiplexed bus. The one exception is that the
address must be driven onto the ADDR[7:0] bus rather than the AD[7:0] bus.
The 12 interrupt sources consist of 8 timers, a far-end signal high alarm, a far-end
signal low alarm, a SNR alarm, and a scrambler synchronization detector. All of
the interrupts are requested on a common pin, IRQ. Each interrupt can be
individually enabled or disabled through the Interrupt Mask Registers
[mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is
determined by reading the Timer Source Register [timer_source; 0x04] and the
IRQ Source Register [irq_source; 0x05].
interrupts cannot be cleared while the alarm is active. In other words, it cannot be
cleared while the condition still exists.
IRQ to be tied to a common interrupt request.
To perform a read, the address of the desired RAM location is first written to
To perform a write, the value to be written is first stored in the Access Data
To ensure reliable access to the embedded RAM, internal read and write
When reading or writing multiple filter coefficients, it may be desirable to
A write operation latches the address from the address-data bus at the falling
The timer interrupt status is set only when the timer transitions to zero. Alarm
IRQ is an open-drain output and must be tied to a pull-up resistor. This allows
Preliminary Information
Specifications. During a read operation, an external
Conexant
2.0 Functional Description
2.5 Microcomputer Interface
Chapter 5.0, Electrical
2-19