RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 20

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

1.0 System Overview
1.2 Pin Descriptions
Table 1-2. Hardware Signal Definitions (2 of 4)
1-8
RST
RQ[1]/
RDAT
RQ[0]/ BCLK
TQ[1]/ TDAT
TQ[0]
QCLK
Pin Label
Reset
Receive Quat 1/
Receive Data
Receive Quat 0/ Bit
Clock
Transmit Quat 1/
Transmit Data
Transmit Quat 0
Quaternary Clock
Signal Name
I/O
O
O
O
I
I
I
Asynchronous, active-low, level-sensitive input that places the transceiver in an
inactive state by setting the power-down mode bit of the Global Modes and
Status Register [global_modes; 0x00], and zeroing the clk_freq [7:0] bits of the
Clock Frequency Select Register [clock_freq;0x20], clk_freq[9,8] bits of the PLL
Modes Register [pll_modes; 0x22], and the hclk_freq[1,0] bits of the Serial
Monitor Source Select Register [serial_monitor_source; 0x01]. All RAM
contents are lost. Does not affect the state of the test access port, which is reset
automatically at power-up only.
RQ[1]/RDAT and RQ[0]/BCLK are bimodal outputs that represent the sign and
magnitude bits of the received quaternary output symbol in parallel channel unit
modes (RQ[1], RQ[0]), and the serial-data and bit-clock outputs in serial
channel unit modes (RDAT, BCLK). Behavior of these outputs is configurable
through the Channel Unit Interface Modes Register [CU_interface_modes;
0x06] for parallel master, parallel slave, serial magnitude-bit-first, and serial
sign-bit-first operations.
(master mode) or the rising/falling edge (programmable) of RBCLK (slave
mode).
TQ[1]/TDAT and TQ[0] are bimodal inputs that represent the sign and magnitude
bits of the quaternary input symbol to be transmitted in parallel channel unit
modes (TQ[1], TQ[0]), and the serial data input in serial channel unit modes
(TDAT). Interpretation of these inputs is configurable through the Channel Unit
Interface Modes Register [CU_Interface_modes; 0x06] for parallel master,
parallel slave, serial magnitude-bit-first and serial sign-bit-first operations.
(master mode) or the rising/falling edge (programmable) of TBCLK (slave
mode).
edge of BCLK.
Runs at the symbol rate. It defines the data on the TQ and RQ interfaces. QCLK
is also used to frame transmit/receive quats in serial mode.
Preliminary Information
For parallel mode operation:
Both outputs are updated at the symbol rate on the rising edge of QCLK
For serial mode operation:
For parallel mode operation:
Both inputs are sampled at the symbol rate on the falling edge of QCLK
For serial mode operation:
TDAT is sampled at the bit rate (two times the symbol rate) on the falling
Channel Unit Interface
RQ[1] = Sign bit output
RQ[0] = Magnitude bit output
RDAT = Serial quaternary data output
BCLK = Bit-rate (two times symbol rate) clock output
RDAT is updated at the bit rate on the rising edge of BCLK
TQ[1] = Sign bit input
TQ[0] = Magnitude bit input
TDAT = Serial quaternary data input
TQ0 = Don’t care (tie or pull up to supply rail)
Conexant
Definition
Single-Chip SDSL/HDSL Transceiver
N8973DSD
RS8973