RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 37

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
N8973DSD
2.3 Timing Recovery and Clock Interface
The timing recovery and clock interface block consists of the timing recovery
circuit, the crystal amplifier, and the clock synthesizer, as detailed in
The main purpose of this circuitry is to generate the internal clocks, including
BCLK and QCLK, from the 10.24 MHz input MCLK, based on the selected data
rate, and to recover the clock from received data. Control fields include the
following:
• Clock Frequency Select Register [clk_select; 0x20]
• PLL Modes Register [clk_select; 0x22]
• hclk_freq[1,0] bits of the Serial Monitor Source Select Register
• PLL Modes Register [pll_modes; 0x22]
• Timing Recovery PLL Phase Offset Register [pll_phase_offsset_low,
• PLL Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E,
See
[serial_monitor_source; 0x01]
pll_phase_offset_high; 0x24, 0x25]
0x5F].
Chapter 3.0,
Preliminary Information
Conexant
Registers, for descriptions of these control fields.
2.3 Timing Recovery and Clock Interface
2.0 Functional Description
Figure
2-5.
2-13