RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 44

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.5 Microcomputer Interface
2.5.4 Reset
2.5.5 Registers
2.5.6 Timers
2-20
The reset input (RST) is an active-low input that places the transceiver in an
inactive state by setting the mode bit (0) in the Global Modes and Status Register
[global_modes; 0x00]. An internal supply monitor circuit ensures that the
transceiver is in an inactive state upon initial application of power to the chip.
The RS8973 has many directly addressable registers that include control and
monitoring functions. Write operations to undefined registers have unpredictable
effects. Read operations from undefined registers have undefined results.
Eight timers are integrated into the RS8973 to control the various on-chip meters
and to aid the microcomputer in stepping through the events of the start-up
sequence.
control circuitry, which determines when the counter is reloaded or decremented.
determines the value from which the timer decrements. There are three 8-bit
registers:
registers corresponds to a timer. Each logic-high bit in timer_restart acts as an
event that causes the corresponding timer to reload. Each logic-high bit in
timer_enable acts to enable the corresponding timer. Each logic-high bit in
timer_continuous acts to reload the counter after timing out.
decrements until it reaches zero. Upon reaching zero, an interrupt is generated if
enabled by the Interrupt Mask Low Register [mask_low_reg, mask_high_reg;
0x02, 0x03]. The interrupt is edge-triggered so that only one interrupt is caused
by a single time-out.
expense of resolution. Only the start-up timers have prescalers.
summary information on the timers.
The structure of each timer includes down counter, zero detect logic, and
For each of the 8 timers, there is a 2-byte timer interval register that
• Timer Restart Register [timer_restart; 0x0C]
• Timer Enable Register [timer_enable; 0x0D]
• Timer Continuous Mode Register [timer_continuous; 0x0E].
These registers control the operation of the timers. Each bit of the 8-bit
Each counter is loaded with the value in its interval register. The counter
A prescaler can precede the timer. This increases the time span available at the
Preliminary Information
Conexant
Single-Chip SDSL/HDSL Transceiver
Table 2-6
N8973DSD
RS8973
provides