RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 41

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
N8973DSD
transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the
use of two internal FIFOs allows an arbitrary phase relationship to QCLK. TQ[1]
and TQ[0] are sampled on the active edge of TBCLK, as programmed through the
MCI. RQ[1] and RQ[0] are output on the active edge of RBCLK, also as
programmed through the MCI.
TBCLK is programmed to be falling-edge active and RBCLK is rising-edge
active.
Figure 2-8. Parallel Slave Mode
The parallel slave mode uses RBCLK and TBCLK inputs to synchronize data
RBCLK
TBCLK
RQ[1]
RQ[0]
TQ[1]
TQ[0]
Preliminary Information
Magnitude
Magnitude
Sign
Sign
Conexant
0
0
0
0
Figure 2-8
Magnitude
Magnitude
Sign
Sign
shows the clock relationships, when
1
1
1
1
2.0 Functional Description
2.4 Channel Unit Interface
Magnitude
Magnitude
Sign
Sign
2
2
2
2
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