RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 55

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A
logical 1 represents the masked condition. A logical 0 represents the unmasked condition. All mask bits behave
identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corresponding
interrupt flag from affecting the IRQ output. Clearing a mask allows the interrupt flag to affect IRQ output.
Unmasking an active interrupt flag will immediately cause the IRQ output to go active, if currently inactive.
Masking an active interrupt flag will cause IRQ to go inactive, if no other unmasked interrupt flags are set.
t4
t3
snr
meter
sut4
sut3
sut2
sut1
Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags.
Individual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg;
0x02].
sync
high_felm
low_felm
low_snr
N8973DSD
0x02—Interrupt Mask Register Low (mask_low_reg)
0x03—Interrupt Mask Register High (mask_high_reg)
—
t4
7
7
General Purpose Timer 4
General Purpose Timer 3
SNR Alarm Timer
Meter Timer
Startup Timer 4
Startup Timer 3
Startup Timer 2
Startup Timer 1
Sync Indication
Far-End Level Meter High Alarm
Far-End Level Meter High Alarm
Signal-to-Noise Ratio Low Alarm
—
t3
6
6
snr
—
5
5
Preliminary Information
meter
—
4
4
Conexant
sut4
sync
3
3
high_felm
sut3
2
2
low_felm
sut2
3.3 Register Description
1
1
3.0 Registers
low_snr
sut1
0
0
3-9