RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 34

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.2 Receive Section
2.2.7 Detector
2-10
2.2.6.3 Error Predictor
2.2.7.2 Peak Detector
2.2.6.2 Feed Forward
2.2.7.3 Error Signals
2.2.6.5 Microcoding
Feedback Equalizer
2.2.6.4 Decision
2.2.7.1 Slicer
Equalizer
The feed forward equalizer (FFE) removes precursors from the received signal.
The FFE can be operated in a special adapt last mode. In this mode, which is
useful during startup, only the last coefficient is updated. The last coefficient is
multiplied with the oldest data sample (sample #7).
The error predictor (EP) improves the performance of the equalizer by
prognosticating errors before they occur.
The decision feedback equalizer (DFE) removes postcursors from the received
signal.
The DAGC, FFE, and EP filters are implemented using an internal
microprogrammable DSP, optimized for LMS filters. Internal DSP
micro-instructions are stored in an on-chip RAM. This microcode RAM is loaded
after power-up through the MCI when the transceiver is initialized.
The detector converts the equalized received signal into a 2B1Q symbol and
produces two error signals used in adapting the receiver equalizers. The signal
detection uses two sub-blocks, a slicer, and a peak detector. Additionally, the
detector contains a scrambler and bit error rate (BER) meter for use during the
start-up sequence.
The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input
to the slicer is the FFE output minus the DFE and EP outputs.
mode, which is used during start-up when the only transmitted symbols are + 3 or
– 3, the slicer threshold is set at zero.
16-bit, 2s complement number, but must be positive and less than 0x2AAA for
proper operation.
The peak detector (PKD) is used only during the two-level transmission part of
start-up. It operates on the echo-free signal. A signal is detected to be a + 3 if it is
higher than both of its neighbors, or a – 3 if it is lower than both of its neighbors.
If neither of the peaked conditions exist, the output of the slicer is used.
The detector computes two error signals for use in the equalizer: a 16-bit slicer
and a 16-bit equalizer.
Other modes, used less often, can be enabled through the MCI:
• A freeze coefficient mode disables the coefficient updates.
• A special mode zeros all of the coefficients.
• Individual FFE coefficients can be read and written through the MCI.
Other modes, used less often, can be enabled through the MCI:
• A freeze coefficient mode disables the coefficient updates.
• A special mode zeros all of the coefficients.
• Individual EP coefficients can be read and written through the MCI.
Other modes, used less often, can be enabled through the MCI:
• A freeze coefficient mode disables the coefficient updates.
• A zero coefficients mode zeros all of the coefficients.
• A zero filter output mode zeros the output of the FIR with no effect on the
• Individual DFE coefficients can be read and written through the MCI.
The slicer can operate in two modes: two-level and four-level. In the two-level
In the four-level mode, the cursor level is specified through the MCI. It is a
coefficients.
Preliminary Information
Conexant
Single-Chip SDSL/HDSL Transceiver
N8973DSD
RS8973