RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 15

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
1.1.1 Transmit Section
1.1.2 Receive Section
N8973DSD
The source of transmitted symbols is programmable through the microcomputer
interface. The primary choices include external 2B1Q-encoded data presented to
the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back
receive symbols from the detector, or a constant “all 1s” source. The symbols are
then optionally scrambled. Isolated pulses can also be generated to support the
testing of pulse templates.
which is highly linear to maximize the echo cancellation and detection properties
of the signal. In addition, the transmit power level of the DAC can be adjusted by
means of the Transmitter Gain Register [tx_gain; 0x29] to optimize performance.
The Transmitter Calibration Register [tx_calibrate; 0x28] contains the nominal
setting for the transmitter gain, which is calibrated and hard-coded at the factory.
The pulse-shaping filters, along with the analog continuous time (CT)
reconstruction filter, then condition the signal to minimize crosstalk to adjacent
subscriber lines. This filtering enables the output signal to meet requirements of
ETSI TS 101 135 (formerly ETR 152) specifications for pulse shape, power
spectral density and output power at 784 kbps, 1168 kbps, and 2320 kbps without
any changes required to external components, including the line transformer.
Finally, the differential line driver provides the current driving capabilities and
low-distortion characteristics needed to drive a large range of subscriber lines.
The differential variable gain amplifier (VGA) receives the data from the
subscriber line. Balancing inputs (RXBP, RXBN) are provided to accommodate
first-order transmit echo cancellation through an external hybrid. The gain is
programmable so that the dynamic range of the analog-to-digital converter (ADC)
can be utilized according to the attenuation of the subscriber line.
of the RS8973. After DC offset cancellation, the impulse shortening (IS) filter
eliminates long tails caused by the line transformer. A replica of the transmit
signal is subtracted from the total receive signal by a digital echo canceller. The
resultant far-end signal is then conditioned by an equalization stage consisting of
automatic gain control (AGC), a feed-forward equalizer, a decision-feedback
equalizer, and an error predictor. A mode-dependent detector is then used to
recover the 2B1Q-encoded data from the equalized signal. The channel unit
interface then provides an optional descrambling function, followed by parallel or
serial output of the sign, and magnitude bits on pins RQ[1,0]/RDAT. A number of
meters are implemented within the receiver to provide average level indications at
various points in the receive signal path. The receive section also performs remote
unit clock recovery through an on-chip phase lock loop (PLL) circuit.
The digital symbols are transformed to an analog signal by means of the DAC,
Digitized receive data is passed to the digital signal processor (DSP) portion
Preliminary Information
Conexant
1.1 Functional Summary
1.0 System Overview
1-3