RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 40

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.4 Channel Unit Interface
2-16
2.4 Channel Unit Interface
The quaternary signals of the channel unit interface have four modes which are
programmable through bits 0 and 1 of the Channel Unit Interface Modes Register
[cu_interface_modes; 0x06]. They are serial sign-bit first, serial magnitude-bit
first, parallel master, and parallel slave.
The sign and magnitude bits of the receive data are output through RDAT on the
rising edge of BCLK. The sign and magnitude bits of the transmit data are
sampled on the falling edge of BCLK at the TDAT input. The sign bit is
transferred first, followed by the magnitude bit of a given symbol in sign-bit first
mode, while the opposite occurs in magnitude-bit first mode. The clock
relationships for serial sign-bit first mode are illustrated in
Figure 2-6. Serial Sign-Bit First Mode
RQ[1] and RQ[0], respectively, on the rising edge of QCLK. The quaternary
transmit data is sampled on the falling edge of QCLK. This clock and data
relationship is illustrated in
Figure 2-7. Parallel Master Mode
Bit-Rate Clock
RQ[1]/TQ[1]
RQ[0]/TQ[0]
In serial mode, a Bit-Rate Clock (BCLK) is output at twice the symbol rate.
In parallel master mode, the sign and magnitude receive data is output through
QCLK
QCLK
BCLK
RDAT
TDAT
Preliminary Information
Sign
Sign
Conexant
Magnitude
0
0
Sign
0
Magnitude
Magnitude
Figure
0
0
0
2-7.
Sign
Sign
Magnitude
Sign
1
1
Single-Chip SDSL/HDSL Transceiver
1
Magnitude
Magnitude
1
1
1
Figure
Sign
Sign
Magnitude
Sign
2
2
2-6.
2
N8973DSD
2
RS8973