RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 97

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RS8973

Manufacturer Part Number
RS8973
Description
Single-chip Sdsl/hdsl Transceiver
Manufacturer
Mindspeed Technologies
Datasheet

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RS8973
Single-Chip SDSL/HDSL Transceiver
Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode
Table 5-11. Channel Unit Interface Timing Requirements, Serial Mode
Table 5-12. Channel Unit Interface Switching Characteristics, Serial Mode
N8973DSD
Symbol
Symbol
NOTE(S):
clocks programmed to falling-edge active.
25
26
27
28
29
30
31
32
33
TDAT setup prior to BCLK falling edge
TDAT hold after BCLK low
BCLK period
BCLK pulse-width high
BCLK pulse-width low
BCLK hold after HCLK rising edge
BCLK delay after HCLK high
RDAT, QCLK hold after BCLK rising edge
RDAT, QCLK delay after BCLK high
TBCLK and RBCLK polarities are programmable through the CU Interface Modes Register. The figure depicts both
Parameter
Parameter
Preliminary Information
Conexant
5.0 Electrical and Mechanical Specifications
T
T
QCLK
QCLK
Minimum
T
QCLK
–50
Minimum
0
5.5 Channel Unit Interface Timing
4 – 20
4 – 20
100
25
2
T
T
QCLK
QCLK
Maximum
T
Maximum
QCLK
50
50
4 + 20
4 + 20
2
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
5-9

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