RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 93

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-4. MCLK Timing Requirements
Figure 5-1. MCLK Timing Requirements
Table 5-5. HCLK Switching Characteristics
N8973DSD
NOTE(S):
(1) If an external clock is applied to XTALI/MCLK, it is referred to as MCLK. Max tolerance = ± 32 ppm.
NOTE(S):
(1) The hclk_freq[1:0] control bits are located in the Serial Monitor Source Select Register [addr. 0x01].
Symbol
Symbol
Edge rates for MCLK are < 5 ns.
4
5
6
7
8
1
2
3
HCLK Period (T
HCLK Period (T
HCLK Period (T
HCLK Pulse-Width High
HCLK Pulse-Width Low
MCLK Period
MCLK Pulse-Width Low
MCLK Pulse-Width High
HCLK
HCLK
HCLK
(1)
MCLK
Parameter
), hclk_freq[1:0] = ‘11’
), hclk_freq[1:0] = ‘00’ or ‘01’
), hclk_freq[1:0] = ‘10’
5.4 Clock Timing
Tables 5-4
characteristics.
clock control timing, respectively.
Parameter
through
Preliminary Information
Figures 5-1
(1)
(1)
3
5-6
Conexant
list the clock timing requirements and switching
(1)
1
and
T
T
HCLK
HCLK
Minimum
T
T
T
Minimum
2
5-2
QCLK
QCLK
QCLK
97.653
35
35
illustrate MCLK timing requirements and
2 – 10
2 – 10
64
16
32
5.0 Electrical and Mechanical Specifications
T
T
T
T
T
Typical
QCLK
QCLK
97.656
Typical
QCLK
HCLK
HCLK
—
—
16
64
32
2
2
T
T
HCLK
HCLK
Maximum
Maximum
T
T
T
QCLK
QCLK
QCLK
97.659
—
—
2 + 10
2 + 10
64
16
32
5.4 Clock Timing
Units
Units
ns
ns
ns
—
—
—
ns
ns
5-5