RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 26

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.1 Transmit Section
2.1.1 Symbol Source Selector/Scrambler
Table 2-1. Symbol Source Selector/Scrambler Modes
2-2
data_source[2:0]
000
001
010
011
100
101
110
111
Isolated pulse. Level selected by isolated_pulse[1,0]. The meter timer must be enabled and in
continuous mode. The pulse repetition interval is determined by the meter timer countdown interval.
Four-level scrambled detector loopback. Sign and magnitude bits from the receiver detector are
scrambled and looped back to the transmitter. Feedback polynomial determined by the htur_lfsr control
bit.
Four-level unscrambled data. Transmits the four-level (2B1Q) sign and magnitude bits from the transmit
channel unit transmit interface without scrambling.
Four-level scrambled 1s. Transmits a scrambled, constant high-logic level as a four-level (2B1Q) signal.
Feedback polynomial determined by the htur_lfsr control bit.
Alternating symbol mode. Outputs symbols of alternating polarity. Level is selected by
isolated_pulse [1:0]. The meter timer must be enabled and in continuous mode. The half period of the
output signal is defined by the meter timer countdown interval.
Four-level scrambled data. Scrambles and transmits the four-level (2B1Q) sign and magnitude bits from
the channel unit transmit interface. Feedback polynomial determined by the htur_lfsr control bit.
Two-level unscrambled data. Constantly forces the magnitude bit from the transmit channel unit
interface to a logic 0, and transmits the resulting two-level signal (as determined by the sign bit)
without scrambling. Valid output levels are limited to + 3 and – 3.
Two-level scrambled 1s. Transmits a scrambled, constant high-logic level as a two-level signal.
Feedback polynomial determined by the htur_lfsr control bit. Scrambler is run at the symbol rate
(half-bit rate) to produce the sign bit of the transmitted signal, while the magnitude bit is sourced with a
constant logic 0. Valid output levels are limited to + 3 and – 3.
The input source selector/scrambler can be configured through the Transmitter
Modes Register [transmitter_modes; 0x0B] data_source [2:0] bits. It selects the
source of the data to be transmitted and determines whether the data is scrambled.
The symbol source selector/scrambler modes are described in
Table
Table 2-2. Four-Level Bit-to-Symbol Conversions
The bit stream is converted into symbols for the four-level cases, as shown in
2-2.
First Input Bit
(Sign)
0
0
1
1
Preliminary Information
Symbol Source Selector/Scrambler Mode
Conexant
Second Input Bit
(Magnitude)
0
1
1
0
Single-Chip SDSL/HDSL Transceiver
Output Symbol
Table
– 3
– 1
+ 1
+ 3
2-1.
N8973DSD
RS8973