RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 62

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Register Description
Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the
corresponding timer is placed in the continuous count mode. While in this mode, after reaching the 0 count, an
enabled timer will reload the contents of its interval register and continue counting. When a mode bit is cleared,
the timer is taken out of the continuous mode. While in this configuration, after reaching the zero count, an
enabled timer will simply stop counting and remain at 0.
For a description of bit-fields, refer to the description given above for register
(timer_enable).
A 1-byte read/write register that is automatically initialized to 0x00 upon RST assertion and initial power
application.
res[6:1]
reg_clk_en
async_mode
A 2-byte read/write register that stores the countdown interval for Startup Timer 1 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
A 2-byte read/write register that stores the countdown interval for Startup Timer 2 in unsigned binary format.
Each increment represents 1024 symbol periods. The contents of this register are automatically loaded into its
associated timer after the timer’s timer_restart bit is set, or after it counts down to zero while in the continuous
mode.
3-16
0x0E—Timer Continuous Mode Register (timer_continuous)
0x0F—Miscellaneous/Test Register (misc_test)
0x10, 0x11—Startup Timer 1 Interval Register (sut1_low, sut1_high)
0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high)
res[6]
t4
7
7
Reserved Bits—Read/write binary field that is automatically initialized to 0x00 upon RST
assertion and initial power application.
Regenerator Clock Enable—When set, it bypasses the frequency synthesizer and timing
recovery. In this mode, the symbol rate equals MCLK
should be set only for the transceiver configured as REG–C in a regenerator configuration.
Refer to
Asynchronous Mode—Read/write control bit that selects asynchronous MCI timing mode,
when set. When reset it selects synchronous mode MCI timing. Refer to
Table 5-13, Microcomputer Interface Timing
Interface Switching
characteristics.
res[5]
t3
6
6
Section 1.3, Regenerator
reg_clk_en
snr
5
5
Characteristics, for MCI timing requirements and switching
Preliminary Information
res[4]
meter
4
4
Conexant
Configuration.
res[3]
sut4
3
3
Requirements, and
÷
16. Normally this bit is reset and
res[2]
sut3
Single-Chip SDSL/HDSL Transceiver
2
2
0x0D—Timer Enable Register
Table 5-14, Microcomputer
res[1]
sut2
1
1
async_mode
N8973DSD
RS8973
sut1
0
0