RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 16

• Manufacturer Part Number: RS8973
• Description: Single-chip Sdsl/hdsl Transceiver
• Manufacturer: Mindspeed Technologies

1.0 System Overview
1.1 Functional Summary
1.1.3 Timing Recovery and Clock Interface
1.1.4 Microcomputer Interface
1.1.5 Test and Diagnostic Interface (JTAG)
1-4
The clock interface includes a crystal amplifier and a clock synthesizer module to
reduce the external components needed for clock generation. The crystal
frequency should be 10.24 MHz.
reference clock based on the data rate, as specified by the Clock Frequency Select
Register [clk_select [7:0]; 0x20] and PLL Modes Register [clk_select [9,8];
0x22]. When configured as a remote unit, the PLL module recovers the incoming
data clock and outputs it on the QCLK pin (on the BCLK pin for serial mode
operation). The HCLK output, which is synchronized to the QCLK signal, can be
configured to cycle at 16, 32, or 64 times the symbol rate.
The microcomputer interface (MCI) provides access to a 256-byte address space
within the transceiver. A combination of direct and indirect addressing methods
are used to access all internal locations. The MCI is designed to interface with
both Intel- and Motorola-style processors with no additional glue logic. A
MOTEL control pin is provided to configure the bus interface control/handshake
lines to conform to common Motorola/Intel conventions. A MUXED control pin
is provided to configure the bus interface address and data lines for multiplexed
or independent data/address bus operation. Little-endian data formatting (least
significant byte of a multibyte word stored at the lowest byte-address location) is
used in all cases, regardless of MOTEL pin selection. A READY control pin is
provided to support wait-state insertion. An Interrupt Request (IRQ) output pin
supports low-latency responses to time-critical events within the transceiver.
transceiver. The timers support various metering functions within the receiver
section and off-load the external microcomputer from complex timing operations
associated with startup procedures. Control and monitoring access to the timers
and meters is provided through the MCI.
The test and diagnostic interface comprises a test access port and a serial monitor
output (SMON). The test access port conforms to IEEE Std 1149.1-1990, (IEEE
Standard Test Access Port and Boundary Scan Architecture). Also referred to as
JTAG, this interface provides direct serial access to each of the transceiver’s I/O
pins. This capability can be used during an in-circuit board test to increase the
testability and reduce the cost of the in-circuit test process.
looking at the transceiver’s internal signals. The programmable signal source is
shifted out serially at 16 times the symbol rate. Most of the receive signal path is
accessible through this output.
The Clock Synthesizer generates the required internal clock from this
Eight 16-bit timers and 10 measurement meters are integrated into the
The serial monitor output can be viewed as a real-time virtual probe for
Preliminary Information
Conexant
Single-Chip SDSL/HDSL Transceiver
N8973DSD
RS8973