RS8973 Mindspeed Technologies, RS8973 Datasheet - Page 107

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RS8973

Manufacturer Part Number
RS8973
Description
Single-chip Sdsl/hdsl Transceiver
Manufacturer
Mindspeed Technologies
Datasheet

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RS8973
Single-Chip SDSL/HDSL Transceiver
Table 5-17. Receiver Requirements and Specifications
Table 5-18. Transmitter Analog Requirements and Specifications (1 of 2)
N8973DSD
Input signals
VGA
Gain step
ADC
Differential voltage range
(full scale input, FS)
Timing recovery PLL pull-in range (digital)
PLL settling time
NOTE(S):
(1) Corresponds to the voltages that produce a full scale reading from the ADC when the VGA gain equals O dB. The input
Transmit symbol rate (f
Pulse template
Input voltage range
Input resistance
Input resistance
Common mode voltage
voltage range is reduced proportionally as VGA gain is increased.
Parameter
(1, 2, 3)
Parameter
(1)
qclk
)
5.8 Analog Specifications
specifications.
two- and three-pair systems.
template for one-pair systems.
bound of the average PSD of 392, 584, and 1160 kbaud systems, respectively.
QCLK frequency (data rate/2)
See
R
L
Tables 5-17
= 135
Figure 5-13
RXP, RXN, RXBP, and RXBN
With respect to VAA/2
@ Data Rate = 2320 kbps
@ Data Rate = 144 kbps
VCOMI
Six gains from 0 dB to +15 dB
(V
Preliminary Information
RXP
Figure 5-13
Comments
and
and
– V
Figure
Conexant
5-18
RXN
Comments
)—(V
list transmitter and receiver analog requirements and
5-14,
and
RXBP
Figure 5-14
Figures 5-15
Table 5-19
– V
RXBN
5.0 Electrical and Mechanical Specifications
)
and
show the transmit pulse template for
Min
72
through
–2.25
2.55
Table 5-20
Min
±64
5.4
5-17
Typ
VAA × 0.4
Typ
show the transmit pulse
3.0
6.0
10
35
10
illustrate the upper
5.8 Analog Specifications
1160
Max
+2.25
Max
3.42
6.6
Units
kHz
ppm
Unit
k
k
ms
dB
V
V
V
5-19
s
P

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